Load-balanced optical packet switching using two-stage time-slot interchangers

A photonic implementation of the load-balanced switch using feed-forward, two-stage optical time-slot interchangers is proposed here. Despite the simplicity of the architecture, preliminary simulations show a packet loss probability comparable to an architecture using FIFO buffers. I Introduction Packet switching in core and edge routers currently relies on electronic switching fabrics, which necessitates expensive optical-electrical-optical conversions. In addition, single-stage switch architectures with centralized scheduling are becoming increasingly impractical as the number of channels and the line rate become higher [1]. These reasons amply justify research on all-optical packet switches. A major drawback of photonics, however, is the lack of optical random access memories. Only simple optical buffers (OBs) using fiber delay lines (FDLs) are feasible at present [2]. The optical Time-Slot-Interchanger (TSI) is a well studied buffering [3]. The basic TSI design comprises a serial input fed by a stream of time-slotted packets; the TSI then produces a serial output out of these packets by permuting their respective time slots. TSIs are key devices in Time-Division Multiplexing (TDM) systems, since switching data among channels actually corresponds to permuting time slots between packets. A very promising packet switch architecture is the so called Load-Balanced Switch (LBS) [4]. It turns out that, internally, this architecture relies on a repetitive interconnection schedule: therefore, if implemented optically, it is likely that some part of the LBS can benefit being assembled out of optical TSIs. We present here a candidate architecture for an optical TSI which efficiently replace the standard FIFO buffers in the electronic version of the LBS. In order to minimize noise and switching losses, the TSI considered here does not contain any internal feed-back loop. II Review of the load-balanced switch architecture The load-balanced switch architecture proposed by C.S. Chang et al. [4] consists of two switch stages and one buffer stage (see Fig. 1). The first switch performs load-balancing; it makes bursty traffic uniformly distributed at the input of the buffer stage. The buffer stage is composed of N independent buffers, each composed in turn of N separate FIFO queues known as Virtual Output Queues (VOQs) because packets are sorted and stored there depending on their output destination (packet destined to output j is stored in VOQ j). The second TDM switch services these queues by periodically connecting each to its corresponding output. The Load-Balancing and TDM stages are in fact alike. Both switching stages run through a periodic sequence of N particular interconnection patterns, Im (with m∈{0,...,N-1}) such that Im connects input i to output (i+m) modulo N. This permutation is set periodically in the LB or TDM stage at the time slots m+kN (where k is any integer). Conversely, at time slot t, input port i is connected to output port j with j=(i+t) mod N. Therefore, during a frame composed of N time slots, each input is connected once to each output (the switch is said to achieve full access). Because the loadbalancing stage equally distributes the traffic load among the inputs of the buffer stage, a deterministic TDM-like schedule that serves every virtual output queue to its corresponding output 1/N of the time gives a 100% throughput if the traffic is weakly mixed [4]. III – Optical implementation of the load-balanced switch. 1Load-balancing stage and TDM stage. A simple architecture to emulate a full-access TDM switch is the stage-controlled banyan network (SC-BN). It is a log2 N multistage interconnection network formed from 2×2 switches. All the N/2 switches within a stage are set either in the bar state or cross state; hence only log2 N control signals are necessary to operate the switch. It has been proven that the set of N permutations obtained from an SC-BN provides full access [5]. Owing to their simplicity, SC-BNs could be monolithically integrated using various photonic technologies such as electroabsorption (EA) modulators, semiconductor optical amplifiers and so forth. Fig. 1. N input × N-output Load-balanced switch architecture. 2Single-stage optical buffer In the case of the LBS architecture, a whole VOQ buffer with N FIFO queues, each of length b, can be emulated by a singlestage TSI that is able to delay packets from 0 to a maximum of bN-1 time slots. Indeed, because interconnection patterns repeat cyclically in the LBS, it is possible to forecast at which time slots an input will be connected to any output: a packet arriving at port r and time slot t will reach its destination d if it is delayed by exactly δ+kN time slots where δ=(d-r-t) mod N, V O Q